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1 typical a pplica t ion fea t ures descrip t ion dual, multiphase current mode synchronous controller for sub-milliohm dcr sensing the lt c ? 3774 is a dual polyphase ? current mode syn- chronous step-down switching regulator controller that drives power blocks, drmos or external gate drivers and power mosfets . it offers an ltc-proprietary technique that enhances the signal-to-noise ratio of the current sense signal, allowing the use of inductors with very low dc winding resistances as the current sense element for maximum efficiency and reduced jitter. the maximum current sense voltage is programmable from 10mv to 30mv. high speed, low offset remote sense differential amplifiers and a precise 0. 6v reference provide accurate output voltages between 0. 6v and 3. 5v from a wide 4. 5v to 38v input supply range. soft recovery from output shorts or overcurrent minimizes output overshoot . burst mode ? operation, continuous and pulse-skipping modes are supported. the constant operating frequency can be synchronized to an external clock or linearly programmed from 200khz to 1. 2mhz. up to six ltc3774 controllers can be paralleled for 1- , 2- , 3- , 4- , 6- , 8- or 12-phase operation. the ltc3774 is available in a 36-lead (5mm 6mm) qfn package. high efficiency dual phase 1.5v/60a step-down converter a pplica t ions n sub-milliohm dcr current sensing n operates with power blocks, drmos or external gate drivers and mosfets n supports phase shedding and n+1 phase redundancy n programmable dcr temperature compensation n 0.75% maximum total dc output error over temperature n dual differential remote output voltage sense amplifiers n phase-lockable fixed frequency range: 200khz to 1.2mhz n v in range: 4.5v to 38v n v out range: 0.6v to 3.5v n supports smooth start-up into pre-biased outputs n programmable soft-start or v out tracking n hiccup mode / soft recovery from output overcurrent n 36-lead (5mm 6mm) qfn package n computer systems n telecom and datacom systems n industrial equipment n dc power distribution systems l, lt , lt c , lt m , linear technology, the linear logo, polyphase and burst mode are registered trademarks and no r sense and hot swap are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5705919, 5929620, 6177787, 6580258, 6498466, 6611131, patent pending. 3774 ta01a v in 4.5v to 20v run1, 2 ilim1, 2 hizb1 hizb2 pwm1 pwmen1 v osns1 ? snsa1 + sns1 ? snsd1 + v osns1 + i th1 phsmd clkout pgood1,2 mode/pllin pwm2 pwmen2 gnd v osns2 ? snsa2 + sns2 ? snsd2 + freq v osns2 + i th2 ltc3774 v in 1/4 intv cc tk/ss2 tk/ss1 intv cc 37.5k 15k drmos drmos f in 500khz 0.33h (0.32m dcr) 0.33h (0.32m dcr) 10k 300f 4v 330f 4v 15k 0.1f 4.7f 2200pf + + v out 1.5v 60a 22f 50v lt c3774 3774fb for more information www.linear.com/ltc3774
2 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in voltage ................................................. C 0. 3v to 40v hizb voltage .............................................. C0. 3v to 40v run , pgood , intv cc voltage ..................... C 0. 3v to 6v sn sa1 + , sn sa2 + , sn sd1 + , sn sd2 + , sn s1 C , sn s2 C ........................ C0. 3v to intv cc intv cc peak output current .................................. 20m a all other pin voltages ........................... C 0. 3v to intv cc operating junction temperature range ( note 2 ) .................................................. C 40 c to 125c storage temperature range .................. C 65 c to 150c (note 1) 11 12 13 14 top view 37 gnd uhe package 36-lead (5mm 6mm) plastic qfn 15 16 17 18 36 35 34 33 32 31 30 29 21 22 23 24 25 26 27 28 8 7 6 5 4 3 2 1itemp2 ith2 v osns2 ? v osns2 + tk/ss2 hizb2 pwmen2 pwm2 run2 gnd itemp1 ith1 v osns1 ? v osns1 + tk/ss1 hizb1 pwmen1 pwm1 run1 gnd ilim2 v in intv cc clkout mode/pllin freq phsmd ilim1 snsd2 + sns2 ? snsa2 + pgood2 pgood1 snsa1 + sns1 ? snsd1 + 20 19 9 10 t jmax = 125c, ja = 43c/w exposed pad (pin 37) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3774euhe#pbf ltc3774euhe#trpbf 3774 36-lead (5mm 6mm) plastic qfn C40c to 125c ltc3774iuhe#pbf ltc3774iuhe#trpbf 3774 36-lead (5mm 6mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ lt c3774 3774fb for more information www.linear.com/ltc3774
3 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 15v, v run = 5v unless otherwise specified. symbol parameter conditions min typ max units main control loop/whole system v in input voltage range 4.5 38 v v out output voltage range l 0.6 3.5 v v osns + regulated feedback voltage i th = 1.2v (note 3) l 595.5 600 604.5 mv i osns + feedback current C30 C100 na v reflnreg reference voltage line regulation v in = 4.5v to 38v 0.002 0.01 %/v v loadreg output voltage load regulation ?i th = 1.2v to 0.7v ?i th = 1.2v to 1.6v l l 0.01 0.01 0.1 0.1 % % g m transconductance amplifier g m i th = 1.2v, sink/source 5a 2 mmho f 0db da unity-gain crossover frequency (note 5) 4 mhz v ovl feedback overvoltage lockout measured at v osns + l 5 7.5 10 % i q input dc supply current normal mode shutdown ( note 4) v run = 0v 9 40 60 ma a df max maximum duty factor in dropout 96 98 % uvlo undervoltage lockout v intvcc falling 3.5 3.75 4.0 v uvlo hys uvlo hysteresis 500 mv i snsa + sense pin bias currents v snsa + = 3.3v 0.5 2 a i snsd + sense pin bias currents v snsd + = 3.3v 30 na i sns C sense pin bias currents v sns C = 3.3v 10 a a vt _sns total sense signal gain to current comparator 5 v/v i temp dcr tempco compensation current v itemp = 0.5v l 27 30 33 a i tk/ss soft-start charge current v tk/ss = 0v l 1 1.25 1.5 a t ss(internal) internal soft-start time v tk/ss = 5v 600 s v hizb hizb pin on threshold v hizb rising 2.2 v v hizb_hys hizb pin on hysteresis 600 mv v run run pin on threshold v run rising l 1.1 1.22 1.34 v v run_hys run pin on hysteresis 80 mv i run run pin pull-up current run < on threshold run > on threshold run < 1.1v run > 1.34v 1 5 a a v sense(max) maximum current sense threshold i th = 2v, v sns C = 3.3v i lim = 0v i lim = 1/4 intv cc i lim = float i lim = 3/4 intv cc i lim = intv cc l l l l l 9.25 14 19 24 28.25 10.25 15 20 25 29.75 11.25 16 21 26 31.25 mv mv mv mv mv power good v pgood(on) pgood pull-down resistance 90 200 ? i pgood(off) pgood leakage current v pgood = 5v C2 2 a t pgood v pgood high to low delay 45 s v pgood pgood trip level v osns + with respect to set output voltage v osns + ramping up v osns + ramping down 5 C5 7.5 C7.5 10 C10 % % lt c3774 3774fb for more information www.linear.com/ltc3774
4 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 15v, v run = 5v unless otherwise specified. symbol parameter conditions min typ max units v pg(hyst) pgood trip level hysteresis 2 % intv cc linear regulator v intvcc linear regulator voltage 6v < v in < 38v 5.3 5.5 5.7 v v ldo int intv cc load regulation i cc = 0ma to 20ma 0.5 2 % oscillator and phase-locked loop f osc oscillator frequency v phsmd = 0v r freq < 23.2k r freq = 30.1k r freq = 47.5k r freq = 54.9k r freq = 75.0k maximum frequency minimum frequency l l 540 1.2 150 250 600 750 1.05 660 0.2 khz khz khz khz mhz mhz mhz i freq freq pin output current v freq = 0.8v 19 20 21 a r mode/pllin mode/pllin input resistance 250 k v mode/pllin pllin input threshold v mode/pllin rising v mode/pllin falling 2 1.2 v v v clkout low output voltage high output voltage i load = C500a i load = 500a 0.2 5.2 v v 2 C 1 channel 1-2 phase delay v phsmd = 0v v phsmd = 1/4 intv cc v phsmd = float v phsmd = 3/4 intv cc v phsmd = intv cc 180 180 180 180 120 deg deg deg deg deg clkout C 1 clkout to channel 1 phase delay v phsmd = 0v v phsmd = 1/4 intv cc v phsmd = float v phsmd = 3/4 intv cc v phsmd = intv cc 60 60 90 45 240 deg deg deg deg deg 1 C clkin channel 1 to clkin phase delay v phsmd = 0v v phsmd = 1/4 intv cc v phsmd = float v phsmd = 3/4 intv cc v phsmd = intv cc 0 90 0 0 0 deg deg deg deg deg pw m /p wmen outputs pwm pwm output high voltage i load = 500a l 5.0 v pwm output low voltage i load = C500a l 0.5 v pwm output current in hi-z state l C5 5 a pwmen pwmen output high voltage i load = 500a l 5.0 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3774 is tested under pulsed load conditions such that t j t a . the ltc3774e is guaranteed to meet performance specifications from 0c to 85c operating junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3774i is guaranteed to meet performance specifications over the full C40c to 125c operating junction temperature range. the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the package thermal impedance and other environmental factors. t j is calculated from the ambient temperature, t a , and power dissipation, p d , according to the following formula: ltc3774uhe: t j = t a + (p d ? 43c/w) note 3: the ltc3774 is tested in a feedback loop that servos v ith to a specified voltage and measures the resultant v fb . note 4: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 5: guaranteed by design. lt c3774 3774fb for more information www.linear.com/ltc3774
5 typical p er f or m ance c harac t eris t ics input quiescent current vs input voltage shutdown current vs input voltage intv cc line regulation oscillator frequency vs input voltage maximum current sense threshold vs common mode voltage maximum current sense threshold vs feedback voltage (current foldback) current sense threshold vs i th voltage common mode voltage (v) 0 maximum current sense threshold (mv) 20 25 30 1.5 2 2.5 3 3774 g01 15 10 0.5 1 3.5 5 0 35 intv cc 3/4 intv cc 1/2 intv cc 1/4 intv cc 0 feedback voltage (v) 0 maximum current sense threshold (mv) 20 25 30 0.2 0.3 0.4 0.5 3774 g02 15 10 0.1 0.6 5 0 35 i lim = 0 i lim = 1/4 intv cc i lim = 1/2 intv cc i lim = 3/4 intv cc i lim = intv cc v(i th ) (v) 0 current sense threshold (mv) 20 25 30 0.75 1 1.51.25 1.75 3774 g03 15 10 5 0 0.25 0.5 2 ?5 ?10 35 i lim = 0 i lim = 1/4 intv cc i lim = 1/2 intv cc i lim = 3/4 intv cc i lim = intv cc input voltage (v) 0 quiescent current (ma) 15 20 3025 35 3774 g04 10 8 6 4 5 10 40 2 0 12 input voltage (v) 0 shutdown current (a) 15 20 3025 35 3774 g05 50 40 30 20 5 10 40 10 0 60 input voltage (v) 0 intv cc voltage (v) 15 20 3025 35 3774 g06 5 4 3 2 5 10 40 1 0 6 input voltage (v) 0 frequency (khz) 15 20 3025 35 3774 g07 1000 800 600 400 5 10 40 200 0 1200 23.2k 47.5k 75k load step (continuous conduction mode) 50s/div 3774 g08 v out = 1.5v 50mv/div ac-coupled i load 5a-div 15a to 30a v in = 12v lt c3774 3774fb for more information www.linear.com/ltc3774
6 typical p er f or m ance c harac t eris t ics power loss tk/ss pull-up current vs temperature run threshold vs temperature regulated feedback voltage vs temperature oscillator frequency vs temperature undervoltage lockout threshold (intv cc ) vs temperature efficiency power loss efficiency i load (a) 0.01 efficiency (%) 10 3774 g09 90 80 60 40 0.1 1 100 20 10 70 50 30 0 100 burst mode pulse-skipping ccm v in = 7v v out = 1.5v i load (a) 0.01 power loss (w) 10 3774 g10 4.5 4.0 3.0 2.0 0.1 1 100 1.0 0.5 3.5 2.5 1.5 0 5.0 burst mode pulse-skipping ccm v in = 7v v out = 1.5v i load (a) 0.01 efficiency (%) 10 3774 g11 90 80 60 40 0.1 1 100 20 10 70 50 30 0 100 v in = 12v v out = 1.5v burst mode pulse-skipping ccm i load (a) 0.01 power loss (w) 10 3774 g12 4.5 4.0 3.0 2.0 0.1 1 100 1.0 0.5 3.5 2.5 1.5 0 5.0 burst mode pulse-skipping ccm v in = 12v v out = 1.5v temperature (c) ?50 i tk/ss (a) 25 3774 g13 1.4 ?25 0 50 125 75 100 150 1.2 1.1 1.3 1 1.5 temperature (c) ?50 run threshold (v) 25 3774 g14 1.3 ?25 0 50 125 75 100 150 1.1 1.0 1.2 0.9 1.4 on off temperature (c) ?50 regulated feedback voltage (mv) 25 3774 g15 603.0 ?25 0 50 125 75 100 150 600.0 598.5 597.0 601.5 595.5 604.5 temperature (c) ?50 frequency (khz) 25 3774 g16 625 ?25 0 50 125 75 100 150 575 550 675 650 525 600 500 700 temperature (c) ?50 3.0 uvlo threshold (v) 3.2 3.6 3.8 4.0 5.0 4.4 0 50 75 3774 g17 3.4 4.6 4.8 4.2 ?25 25 100 125 150 rise fall lt c3774 3774fb for more information www.linear.com/ltc3774
7 typical p er f or m ance c harac t eris t ics prebiased output at 0.5v quiescent current vs temperature shutdown current vs temperature freq pin source current vs temperature temperature (c) ?50 quiescent current (ma) 25 3774 g18 9.75 ?25 0 50 125 75 100 150 9.25 9.50 9.00 8.50 8.25 8.75 8.00 10.00 temperature (c) ?50 shutdown current (a) 25 3774 g19 55 ?25 0 50 125 75 100 150 45 50 40 30 25 35 20 60 temperature (c) ?50 freq pin current (a) 25 3774 g20 ?25 0 50 125 75 100 150 21.0 20.5 19.5 19.0 20.0 18.5 21.5 50ms/div 3774 g08 v out 500mv/div track/ss 500mv/div lt c3774 3774fb for more information www.linear.com/ltc3774
8 p in func t ions pgood1, pgoo d2 (pin 15, pin 14): power good indica - tor outputs. open drain outputs that pull to ground when output voltage is not in regulation . snsa1 + , snsa2 + ( pin 16, pin 13): ac current sense comparator (+) inputs. this input senses the signal from the output inductors dcr with a filter bandwidth of five times larger than the inductors l/dcr value. sns1 C , sns2 C ( pin 17, pin 12): negative current sense inputs. the negative input of the current comparator is normally connected to the output. snsd1 + , snsd2 + ( pin 18, pin 11): dc current sense comparator (+) inputs. this input senses the signal from the output inductors dcr with a filter bandwidth equal to the inductors l/dcr value. run1, ru n2 (pin 20, pin 9): run control inputs. a volt - age above 1.22v turns on the ic. there is a 1a pull-up current on this pin . once the run pin rises above the 1.22v threshold the pull-up increases to 5a. pmw1, pw m2 ( pin 21, pin 8): ( top ) gate signal outputs. this signal goes to the pwm or top gate input of the ex - ternal gate driver or integrated driver mosfet or power block . this is a three-state compatible output. p wmen1, pwme n2 (pin 22, pin 7): enable pins for non- three-state compatible drivers. this pin has an internal open-drain pull-up to intv cc . an external resistor to gnd is required. this pin is low when the corresponding pwm pin is high impedance. hizb1, hiz b2 (pin 23, pin 6): phase shedding input pins. when this pin is low, the corresponding pwm pin goes high impedance and pwmen goes low . tie to intv cc or v in to disable this function. tk/ss1, tk /ss2 (pin 24, pin 5): output voltage tracking and soft-start inputs. the voltage ramp rate at this pin sets the voltage ramp rate of the output. a capacitor to ground accomplishes soft-start. this pin has a 1.25a pull-up current. v osns1 + , v osns2 + ( pin 25, pin 4): remote sense differ - ential amplifier non-inverting inputs. connect to feedback divider center tap with the divider across the output load . the remote sense differential amplifier s output is internally connected to the error amplifier inverting input. v osns1 C , v osns2 C ( pin 26, pin 3): remote sense differ - ential amplifier inverting inputs. connect to sense ground at the output load . ith1, it h2 (pin 27, pin 2): current control thresholds and error amplifier compensation points. the current comparators threshold increases with the ith control voltage. itemp1, item p2 (pin 28, pin 1): input of the temperature sensing comparators. connect this pin to an external ntc resistor placed near the inductors. floating this pin disables the dcr temperature compensation function. ilim1, ili m2 (pin 29, pin 36): current comparator sense voltage limit selection pins. phsmd ( pin 30): phase mode pin. this pin selects ch1- ch2 and ch1-clkout phase relationships. freq ( pin 31 ): frequency set / select pin . a resistor between this pin and gnd sets the switching frequency . this pin sources 20ua. mode/pllin ( pin 32): dual function pin. tying this pin to gnd, intv cc or floating it enables forced continuous mode, pulse-skipping mode or burst mode operation re - spectively. applying a clock signal to this pin causes the internal pll to synchronize the internal oscillator to the clock signal and for ces for ced continuous mode. the pll compensation network is integrated on to the ic. clkout ( pin 33 ): clock output pin. this pin is used to synchronize other ltc3774s. intv cc ( pin 34): internal 5.5v regulator output. the con - trol circuits are powered from this voltage . decouple this pin to gnd with a minimum of 4.7f low esr tantalum or ceramic capacitor. this pin is intended to be used as a reference only. please do not bias other applications off this voltage! v in ( pin 35): main input supply. decouple this pin to gnd with a capacitor (0.1f to 1f) gnd ( pins 19, 10, exposed pad pin 37): ground. all small-signal components and compensation components should be connected here. the exposed pad must be soldered to the pcb ground for electrical connection and rated thermal performance. lt c3774 3774fb for more information www.linear.com/ltc3774
9 func t ional b lock diagra m ? + ? ++ sleep intv cc 0.55v note: functional block diagram shows 1 channel only. the 2 channels are identical. ? + ? + 0.5v ss ? + 1.22v run 1.25a v in ea ith r c c c1 c ss run tk/ss 0.6v ref s r q phsmd 5.5v reg active clamp osc mode/sync detect slope compensation uvlo 1 r i thb 1a/5a freq clkout mode/pllin itemp 0.6v burst en ilim ? + ? + i cmp i rev f ? + ? + ov uv ? + diffamp ? + amp 0.555v pgood sns ? snsa + pwm intv cc v osns ? v osns + snsd + 3774 bd gnd 0.645v 20k 20k ov run on fcnt pll-sync tempsns v in sns ? 1/2 pwmen switch logic hizb intv cc lt c3774 3774fb for more information www.linear.com/ltc3774
10 o pera t ion main control loop the ltc3774 uses an ltc proprietary current sensing , current mode step-down architecture . during normal operation, the top mosfet is turned on every cycle when the oscillator sets the rs latch, and turned off when the main current comparator, i cmp , resets the rs latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the ith pin, which is the output of the error amplifier, ea. the remote sense amplifier ( diffamp) produces a signal equal to the differential voltage sensed across the output capacitor divided down by the feedback divider and re-references it to the local ic ground reference. the error amplifier receives this feedback signal and compares it to the internal 0.6v reference. when the load current increases, it causes a slight decrease in the v osns + pin voltage relative to the 0.6v reference, which in turn causes the ith voltage to increase until the inductors average current equals the new load current . after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator, i rev , or the beginning of the next cycle. the main control loop is shut down by pulling the run pin low. releasing run allows an internal 1.0a current source to pull up the run pin . when the run pin reaches 1.22v, the main control loop is enabled and the ic is powered up. when the run pin is low, all functions are kept in a controlled state. sensing signal of very low dcr the ltc3774 employs a unique architecture to enhance the signal-to-noise ratio that enables it to operate with a small sense signal of a very low value inductor dcr , 1m or less, to improve power efficiency, and reduce jitter due to the switching noise which could corrupt the signal. the ltc3774 can sense a dcr value as low as 0. 2m with careful pcb layout. the ltc3774 comprises two positive sense pins, snsd + and snsa + , to acquire signals and processes them internally to provide the response as with a dcr sense signal that has a 14db signal-to-noise ratio improvement. in the meantime, the current limit threshold is still a function of the inductor peak current and its dcr value, and can be accurately set from 10mv to 30mv in 5mv steps with the ilim pin. the filter time constant, r1c1, of the snsd + should match the l/ dcr of the output inductor, while the filter at snsa + should have a bandwidth of five times larger than snsd + , r2 ? c2 equals r1 ? c1 /5. internal soft-start by default, the start-up of the output voltage is normally controlled by an internal soft-start ramp. the internal soft- start ramp represents a noninverting input to the error amplifier. the v osns + pin is regulated to the lower of the error amplifiers three noninverting inputs (the internal soft-start ramp, the tk/ss pin or the internal 600mv ref - erence). as the ramp voltage rises from 0v to 0.6v over approximately 600s, the output voltage rises smoothly from its prebiased value to its final set value. certain applications can result in the start-up of the con - verter into a non-zero load voltage, where residual charge is stored on the output capacitor at the onset of converter switching. in order to prevent the output from discharging under these conditions, the bottom mosfet is disabled until soft-start is greater than v osns + . shutdown and start-up (run and tk/ss pins) the ltc3774 can be shut down using the run pin. pulling the run pin below 1.14v shuts down the main control loop for the controller and most internal circuits , including the intv cc regulator. releasing the run pin allows an internal 1.0a current to pull up the pin and enable the controller. alternatively, the run pin may be externally pulled up or driven directly by logic. be careful not to exceed the absolute maximum rating of 6v on this pin. the start-up of the controllers output voltage, v out , is controlled by the voltage on the tk/ss pin. when the voltage on the tk/ss pin is less than the 0.6v internal reference, the ltc3774 regulates the v osns + voltage to the tk/ss pin voltage instead of the 0.6v reference. this allows the tk/ss pin to be used to program a soft-start by connecting an external capacitor from the tk /ss pin to gnd. an internal 1.25a pull-up current charges this capacitor, creating a voltage ramp on the tk/ss pin. as the tk/ss voltage rises linearly from 0v to 0.6v (and beyond), the output voltage, v out , rises smoothly from zero to its final value . alternatively, the tk/ ss pin can be lt c3774 3774fb for more information www.linear.com/ltc3774
11 o pera t ion used to cause the start-up of v out to track that of another supply. typically, this requires connecting to the tk/ss pin an external resistor divider from the other supply to ground ( see the applications information section). when the run pin is pulled low to disable the controller, or when intv cc drops below its undervoltage lockout threshold of 3.75v, the tk/ss pin is pulled low by an internal mosfet. when in undervoltage lockout , the controller is disabled and the external mosfets are held off. light load current operation (burst mode operation, pulse-skipping or continuous conduction) the ltc3774 can be enabled to enter high efficiency burst mode operation, constant-frequency pulse-skipping mode or forced continuous conduction mode . to select forced continuous operation , tie the mode pin to gnd. to select pulse-skipping mode of operation, tie the mode/pllin pin to intv cc . to select burst mode operation, float the mode/pllin pin. when the controller is enabled for burst mode operation , the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifier, ea, will decrease the voltage on the i th pin . when the i th voltage drops below 0.5v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the ea s output begins to rise . when the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator . when the controller is enabled for burst mode operation, the inductor current is not allowed to reverse . the reverse current comparator (i rev ) turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from re - versing and going negative. thus, the controller operates in discontinuous operation . in for ced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the i th pin, just as in normal operation. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. when the mode/ pllin pin is connected to intv cc , the ltc3774 operates in pwm pulse skipping mode at light loads. at very light loads, the current comparator, i cmp , may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse ( discontinuous operation). this mode, like forced continuous operation , exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode , but not nearly as high as burst mode operation. frequency selection and phase-locked loop (freq and mode/pllin pins) the selection of switching frequency is a trade-off between efficiency and component size . low frequency opera - tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. if the mode/pllin pin is not being driven by an external clock source , the freq pin can be used to program the controllers operating frequency from 200khz to 1.2mhz. there is a precision 20a current flowing out of the freq pin so that the user can program the controllers switching frequency with a single resistor to gnd. a curve is provided later in the applications information section showing the relationship between the voltage on the freq pin and switching frequency. a phase-locked loop (pll) is available on the ltc3774 to synchronize the internal oscillator to an external clock source that is connected to the mode /pllin pin. the pll loop filter network is integrated inside the ltc3774. the phase - locked loop is capable of locking any frequency within the range of 200khz to 1. 2mhz. the frequency setting resistor should always be present to set the controllers initial switching frequency before locking to the external clock. the controller operates in forced continuous mode when it is synchronized. lt c3774 3774fb for more information www.linear.com/ltc3774
12 ltc3774 3774 f01a mode/pllin phsmd +240 clkout ltc3774 0,120 240,60 mode/pllin phsmd clkout intv cc ltc3774 3774 f01b mode/pllin phsmd +90 clkout ltc3774 0,180 90,270 mode/pllin phsmd clkout ltc3774 mode/pllin phsmd +60 clkout ltc3774 0,180 60,240 mode/pllin phsmd clkout 3774 f01c +60 ltc3774 120,300 mode/pllin phsmd clkout ltc3774 3774 f01d mode/pllin phsmd +90 clkout ltc3774 135,315 ltc3774 mode/pllin phsmd 3/4 intv cc +45 clkout 90,270 ltc3774 mode/pllin phsmd +90 clkout 0,180 225,45 mode/pllin phsmd clkout o pera t ion figure 1a. 3-phase operation figure 1b. 4-phase operation figure 1c. 6-phase operation figure 1d. 8-phase operation figure 1e. 12-phase operation ltc3774 mode/pllin phsmd +60 clkout ltc3774 0,180 60,240 mode/pllin phsmd clkout +60 ltc3774 120,300 mode/pllin phsmd clkout ltc3774 mode/pllin phsmd 1/4 intv cc +60 clkout ltc3774 150,330 210,30 mode/pllin phsmd clkout 3774 f01e +60 ltc3774 270,90 mode/pllin phsmd clkout lt c3774 3774fb for more information www.linear.com/ltc3774
13 o pera t ion multiphase operation for output loads that demand high current , multiple ltc3774 s can be daisychained to run out of phase to provide more output current without increasing input and output voltage ripple. the mode/ pllin pin allows the ltc3774 to synchronize to the clkout signal of another ltc3774. the clkout signal can be connected to the mode / pllin pin of the following ltc3774 stage to line up both the frequency and the phase of the entire system. tying the phsmd pin to intv cc , gnd or floating it generates a phase difference (between ch1 and clkout) of 240, 60 or 90 respec- tively, and a phase difference (between ch1 and ch2) of 120 , 180 or 180. tying phsmd to 1/ 4 or 3/ 4 of intv cc generates a phase difference of 60 and 45 between ch1 and clkout. figure 1 shows the phsmd connections necessary for 3-, 4-, 6-, 8- or 12-phase operation. a total of 12 phases can be daisychained to run simultaneously out of phase with respect to each other. sensing the output voltage with a differential amplifier the lt c3774 includes a low offset , high input impedance, unity-gain, high bandwidth differential amplifier for ap - plications that require true remote sensing. sensing the load across the load capacitors directly benefits regulation in high current, low voltage applications, where board interconnection losses can be a significant portion of the total error budget. connect v osns + to the center tap of the feedback divider across the output load, and v osns C to the load ground. see figure 2. the ltc3774 differential amplifier is configured for unity gain, meaning that the difference between v osns + and v osns C is translated to its output, relative to gnd. the differential amplifiers output is internally connected to the error amplifier inverting input. care should be taken to route the v osns + and v osns C pcb traces parallel to each other all the way to the remote sens - ing points on the board . in addition, avoid routing these sensitive traces near any high speed switching nodes in the cir cuit . ideally, the v osns + and v osns C traces should be shielded by a low impedance ground plane to maintain signal integrity. figure 2. differential amplifier connection ltc3774 feedback divider v osns + c f1 r d1 c out1 c out2 v out 10 r d2 v osns ? 3774 f02 10 ? + diffamp lt c3774 3774fb for more information www.linear.com/ltc3774
14 o pera t ion power good (pgood pin) the pgood pin is connected to the open drain of an inter - nal n-channel mosfet. the mosfet turns on and pulls the pgood pin low when the v osns + pin voltage is not within 7.5% of the 0.6v reference voltage. the pgood pin is also pulled low when the run pin is below 1.14v or when the ltc3774 is in the soft-start or tracking up phase. when the v osns + pin voltage is within the 7.5% regulation window, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6v. the pgood pin will flag power good immediately when the v osns + pin is within the regulation window. however, there is an internal 45s power-bad mask when the v osns + goes out of the window. output overvoltage protection an overvoltage comparator , ov, guards against transient overshoots (>7.5%) as well as other more serious condi - tions that may overvoltage the output . in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the over voltage condition is cleared. undervoltage lockout the ltc3774 has two functions that help protect the controller in case of undervoltage conditions . a precision uvlo comparator constantly monitors the intv cc voltage to ensure that an adequate gate-drive voltage is present. it locks out the switching action when intv cc is below 3.75v. to prevent oscillation when there is a disturbance on the intv cc , the uvlo comparator has 500mv of preci - sion hysteresis. another way to detect an under voltage condition is to monitor the v in supply. because the run pin has a preci - sion turn-on reference of 1.22v, one can use a resistor divider to v in to turn on the ic when v in is high enough. an extra 4a of current flows out of the run pin once the run pin voltage passes 1.22v. the run comparator itself has about 80mv of hysteresis . one can program additional hysteresis for the run comparator by adjusting the values of the resistive divider. for accurate v in undervoltage detection, v in needs to be higher than 4.75v. always set the v in undervoltage detection threshold higher than the power stage uvlo threshold so that the ltc3774 is enabled after the power stage is. lt c3774 3774fb for more information www.linear.com/ltc3774
15 a pplica t ions i n f or m a t ion the typical application on the first page of this data sheet is a basic ltc3774 application circuit. the ltc3774 is designed and optimized for use with a very low dcr value by utilizing a novel approach to reduce the noise sensitivity of the sensing signal by a factor of 14db. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. however, as the dcr value drops below 1m, the signal-to-noise ratio is low and current sensing is difficult . ltc3774 uses an ltc proprietary technique to solve this issue. in general, external component selection is driven by the load require - ment, and begins with the dcr and inductor value. next, power mosfets are selected . finally, input and output capacitors are selected. current limit programming the ilim pin is a 5- level logic input which sets the maxi - mum current limit of the controller. when ilim is either grounded , floated or tied to intv cc , the typical value for the maximum current sense threshold will be 10mv, 20mv or 30mv, respectively. setting ilim to one-fourth intv cc and three-fourths intv cc for maximum current sense thresholds of 15mv and 25mv. setting i lim using a resistor divider off of intv cc will allow the maximum current sense threshold setting to not change when the 5.5v ldo is in dropout at start-up. please note that the i lim pin has an internal 500k pull-down to gnd and a 500k pull-up to intv cc . which setting should be used? for the best current limit accuracy, use the highest setting that is applicable to the output requirements. snsd + , snsa + and sns C pins the snsa + and sns C pins are the inputs to the current comparators, while the snsd + pin is the input of an internal amplifier . the operating input voltage range is 0v to 3.5v for all three sense pins. all the positive sense pins that are connected to the current comparator or the amplifier are high impedance with input bias currents of less than 1a, but there is also a resistance of about 300k from the sns C pin to ground. the sns C should be connected directly to v out . the snsd + pin connects to the filter that has a r1 ? c1 time constant matched to l/dcr of the inductor. the snsa + pin is connected to the second filter with the time constant one-fifth that of r1 ? c1. care must be taken not to float these pins during normal operation. filter components, especially capacitors, must be placed close to the ltc3774, and the sense lines should run close together to a kelvin con - nection underneath the current sense element (figure?3). because the ltc3774 is designed to be used with a very low dcr value to sense inductor current, without proper care, the parasitic resistance, capacitance and inductance will degrade the current sense signal integrity, making the programmed current limit unpredictable . as shown in figure 4, resistors r1 and r2 are placed close to the output inductor and capacitors c1 and c2 are close to the ic pins to prevent noise coupling to the sense signal. figure 3. sense lines placement with inductor dcr c out to sense filter, next to the controller inductor 3774 f03 lt c3774 3774fb for more information www.linear.com/ltc3774
16 a pplica t ions i n f or m a t ion the ltc3774 could also be used like any typical current mode controller by disabling the snsd + pin, shorting it to ground. an r sense resistor or a rc filter can be used to sense the output inductor signal and connects to the snsa + pin . if the rc filter is used, its time constant , r ? c , is equaled to l/dcr of the output inductor. in these applications, the current limit, v sense (max) , will be five times larger for the specified ilim, and the operating voltage range of snsa + and sns C is from 0v to 5.25v. inductor dcr sensing the ltc3774 is specifically designed for high load current applications requiring the highest possible efficiency; it is capable of sensing the signal of an inductor dcr in the sub milliohm range (figure 4). the dcr is the dc winding resistance of the inductor s copper , which is often less than 1m for high current inductors. in high current and low output voltage applications, a conduction loss of a high dcr or a sense resistor will cause a significant reduction in power efficiency. for a specific output requirement, chose the inductor with the dcr that satisfies the maxi - mum desirable sense voltage, and uses the relationship of the sense pin filters to output inductor characteristics as depicted below . dcr = v sense(max) i max + ? i l 2 l/dcr = r1? c1 = 5 ? r2 ? c2 where: v sense(max) : maximum sense voltage for a given ilim threshold i max : maximum load current ?i l : inductor ripple current l, dcr: output inductor characteristics r1 ? c1: filter time constant of the snsd + pin r2 ? c2: filter time constant of the snsa + pin figure 4. inductor dcr current sensing v in v in pwm itemp r ntc 100k inductor dcrl snsd + snsa + sns ? gnd ltc3774 v out 3774 f04 r1 c1 c2 place c1, c2 next to ic place r1, r2 next to inductor r1c1 = 5 ? r2c2 r s 20k r itemp r p 43.2k r2 ltc4449 5v v logic v cc in boost tg ts bg lt c3774 3774fb for more information www.linear.com/ltc3774
17 a pplica t ions i n f or m a t ion to ensure that the load current will be delivered over the full operating temperature range, the temperature coefficient of dcr resistance, approximately 0.4%/c, should be taken into account . the ltc3774 features a dcr temperature compensation circuit that uses an ntc temperature sensing resistor for this purpose. see the inductor dcr sensing temperature compensation section for details. typically, c1 and c2 are selected in the range of 0.047f to 0.47f. if c1 and c2 are chosen to be 220nf, and an inductor of 330nh with 0.32m dcr is selected , r1 and r2 will be 4.7k and 942 respectively. the bias current at snsd + and snsa + is about 30na and 500na respectively, and it causes some small error to the sense signal. there will be some power loss in r1 and r2 that relates to the duty cycle, and will be the most in continuous mode at the maximum input voltage: p loss r ( ) = v in(max) C v out ( ) ? v out r ensure that r1 and r2 have a power rating higher than this value. however, dcr sensing eliminates the conduction loss of a sense resistor; it will provide a better efficiency at heavy loads. to maintain a good signal-to-noise ratio for the current sense signal , using a minimum ?v sense of 2mv for duty cycles less than 40% is desirable. the actual ripple voltage will be determined by the following equation : ? v sense = v out v in ? v in C v out r1 ? c1 ? f osc inductor dcr sensing temperature compensation and the itemp pin inductor dcr current sensing provides a lossless method of sensing the instantaneous current. therefore, it can provide higher efficiency for applications of high output currents. however, the dcr of the inductor, which is the small amount of dc winding resistance of the copper , typically has a positive temperature coefficient. as the temperature of the inductor rises, its dcr value increases. the current limit of the controller is therefore reduced. the ltc3774 offers a method to counter this inaccuracy by allowing the user to place an ntc temperature sensing resistor near the inductor to actively correct this error. the itemp pin, when left floating, is at a voltage around 5v and dcr temperature compensation is disabled . the itemp pin has a constant 30a precision current flowing out the pin. by connecting an ntc resistor from the itemp pin to sgnd, the maximum current sense threshold can be varied over temperature according the following equation: v sensemax(adj) = v sense(max) ? 2 ? v itemp 2.8 1.5 where: v sensemax( adj) is the maximum adjusted current sense threshold. v sense(max) is the maximum current sense threshold specified in the electrical characteristics table. it is typi - cally 30mv , 25mv, 20mv, 15mv or 10mv depending on the setting i lim pins. v itemp is the voltage of the itemp pin. the valid voltage range for dcr temperature compensation on the itemp pin is 1.4v to 0.6v, with 1.4v or above being no dcr temperature correction and 0.6v the maximum correction. however, if the duty cycle of the controller is less than 25%, the itemp range is extended from 1.4v to 0v. the ntc resistor has a negative temperature coefficient, meaning its value decreases as temperature rises. the v itemp voltage , therefore , decreases as temperature lt c3774 3774fb for more information www.linear.com/ltc3774
18 a pplica t ions i n f or m a t ion increases and in turn , the v sensemax(adj) will increase to compensate the dcr temperature coefficient. the ntc resistor, however, is nonlinear and the user can linear - ize its value by building a resistor network with regular resistors. consult the ntc manufacturers data sheets for detailed information. another use for the itemp pins, in addition to ntc com - pensated dcr sensing, is adjusting v sense(max) to values between the nominal values of 10mv, 15mv, 20mv, 25mv and 30mv for a more precise current limit. this is done by applying a voltage less than 1. 4v to the itemp pin. v sense(max) will be varied per the previous equation and the same duty cycle limitations will apply. the current limit can be adjusted using this method either with a sense resistor or dcr sensing . ntc compensated dcr sensing for dcr sensing applications where a more accurate current limit is required, a network consisting of an ntc thermistor placed from the itemp pin to ground will provide correction of the current limit over temperature. figure 4 shows this network. resistors r s and r p will linearize the impedance the itemp pin sees. to implement ntc compensated dcr sensing, design the dcr sense filter network per the same procedure mentioned in the previous selection, except calculate the divider components using the room temperature value of the dcr. 1. set the itemp pin resistance to 46.7k at 25c. with 30a flowing out of the itemp pin, the voltage on the itemp pin will be 1.4v at room temperature. current limit correction will occur for inductor temperatures greater than 25c. 2. calculate the itemp pin resistance and the maximum inductor temperature which is typically 100c. use the equations: r itemp100c = v itemp100c 30a v itemp100c = 1.4v ? 4.2 i max ? dcr(max) ? r2 / r1 + r2 ( ) ? 100 c ? 25 c ( ) ? 0.4 / 100 v sense(max) calculate the values for r p and r s . a simple method is to graph the following r s versus r p equations with r s on the y-axis and r p on the x-axis. r s = r itemp25c C r ntc25c || r p r s = r itemp100c C r ntc100c || r p next, find the value of r p that satisfies both equations which will be the point where the curves intersect . once r p is known, solve for r s . the resistance of the ntc thermistor can be obtained from the vendors data sheet either in the form of graphs, tabulated data or formulas. the approximate value for the ntc thermistor for a given temperature can be calculated from the following equation: r = r o ? exp b ? 1 t + 273 ? 1 t o + 273 ? ? ? ? ? ? ? ? ? ? ? ? where: r = resistance at temperature t , which is in degrees c r o = resistance at temperature t o , typically 25c b = b-constant of the thermistor. figure 5 shows a typical resistance cur ve for a 100k thermistor and the itemp pin network over temperature. starting values for the ntc compensation network are listed below: ? ntc r o = 100k ? r s = 20k ? r p = 50k but, the final values should be calculated using the above equations and checked at 25c and 100c. lt c3774 3774fb for more information www.linear.com/ltc3774
19 after determining the components for the temperature compensation network, check the results by plotting i max versus inductor temperature using the following equations: i max = v sensemax(adj) ? ? v sense / 2 dcr(max) at 25 c ? 1 + t l(max) ? 25 c ( ) ? 0.4 / 100 ( ) where: v sensemax(adj) = v sense(max) ? 2.0v ? v itemp 2.8 1.5 v itemp = 30a ? r s + r p ||r ntc ( ) use typical values for v sense(max) . the resulting current limit should be greater than or equal to i max for inductor temperatures between 25 c and 100 c. these are typical values for the ntc compensation network: ? ntc r o = 100k, b-constant = 3000 to 4000 ? r s 20k ? r p 50k generating the i max versus inductor temperature curve plot first using the above values as a starting point and then adjusting the r s and r p values as necessary is another a pplica t ions i n f or m a t ion approach. figure 6 shows a typical curve of i max versus inductor temperature. the same thermistor network can be used to correct for temperatures less than 25c. but make sure v itemp is greater than 0.6v for duty cycles of 25% or more, oth - erwise temperature correction may not occur at elevated ambients . for the most accurate temperature detection, place the thermistors next to the inductor as shown in figure 7. take care to keep the itemp pin away from the switch nodes. inductor temperature (c) 10 resistance (k) 100 1000 10000 ?40 20 40 60 10080 120 1 ?20 0 3774 f05 thermistor resistance r o = 100k t o = 25c b = 4334 for 25c/100c r itemp r s = 20k r p = 43.2k 100k ntc figure 5. resistance versus temperature for the itemp pin network and the 100k ntc inductor temperature (c) ?40 i max (a) 15 20 25 20 60 120 3774 f06 10 5 0 ?20 0 40 80 100 corrected i max nominal i max uncorrected i max r s = 20k r p = 43.2k ntc thermistor: r o = 100k t o = 25c b = 4334 v out r ntc l1 sw1 3774 f07 figure 6. worst-case i max versus inductor temperature curve with and without ntc temperature compensation figure 7. thermistor location. place thermistor next to inductor for accurate sensing of the inductor temperature, but keep the itemp pin away from the switch nodes and gate drive traces lt c3774 3774fb for more information www.linear.com/ltc3774
20 a pplica t ions i n f or m a t ion pre-biased output start-up there may be situations that require the power supply to start up with a pre-bias on the output capacitors . in this case, it is desirable to start up without discharging that output pre-bias. the ltc3774 can safely power up into a pre-biased output without discharging it. the ltc3774 accomplishes this by disabling both the top and bottom mosfets until the tk /ss pin voltage and the internal soft-start voltage are above the v osns + pin volt - age. when v osns + is higher than tk/ss or the internal soft-start voltage , the error amp output is railed low. the control loop would like to turn the bottom mosfet on, which would discharge the output. disabling both top and bottom mosfets prevents the pre-biased output voltage from being discharged. when tk/ss and the internal soft-start both cross 500mv or v osns + , whichever is lower, both top and bottom mosfets are enabled. if the pre-bias is higher than the ov threshold, the bottom gate is turned on immediately to pull the output back into the regulation window. overcurrent fault recovery when the output of the power supply is loaded beyond its preset current limit, the regulated output voltage will col - lapse depending on the load. the output may be shorted to ground through a ver y low impedance path or it may be a resistive short , in which case the output will collapse partially, until the load current equals the preset current limit. the controller will continue to source current into the short. the amount of current sourced depends on the ilim pin setting and the v osns + voltage as shown in the current foldback graph in the typical performance characteristics section. upon removal of the short, the output soft starts using the internal soft-start, thus reducing output overshoot. in the absence of this feature, the output capacitors would have been charged at current limit, and in applications with minimal output capacitance this may have resulted in output overshoot. current limit foldback is not disabled during an overcurrent recovery . the load must step below the folded back current limit threshold in order to restart from a hard short. phase shedding/n+1 redundancy (hizb pin) unlike the run pins, the hizb pins cause the pwm to enter its high impedance state while not pulling down on ith or tk/ss. this allows two possibilities: first, one can shed a phase based on load requirements via the hizb pin. this im - proves low current efficiency in a single output multiphase case by reducing switching losses . second , for applications that require n+1 redundancy, it is now easy to disconnect a channel with damaged mosfets or drivers . when com - bined with a hot swap? controller, such as the ltc4226, the hizb pin could be connected to the gate of the hot swap switch . when a damaged mosfet triggers the hot swap controller, it also disables the corresponding chan - nels power stage, disconnecting it. since ith and tk /ss are unaffected, it does not affect the rest of the system. the propagation delay from hizb falling to high impedance on p wm is <200ns. inductor value calculation given the desired input and output voltages, the inductor value and operating frequency , f osc , directly determine the inductors peak-to-peak ripple current: i ripple = v out v in v in C v out f osc ? l ? ? ? ? ? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest efficiency operation is obtained at low frequency with a small ripple current . achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40 % of i out(max) . note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: l v in C v out f osc ? i ripple ? v out v in lt c3774 3774fb for more information www.linear.com/ltc3774
21 inductor core selection once the inductance value is determined, the type of in - ductor must be selected . core loss is independent of core size for a fixed inductor value , but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies , so design goals can con - centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc - tance collapses abruptly when the peak design current is exceeded . this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! pwm and pwmen pins the pwm pins are three-state compatible outputs , de - signed to drive mosfet drivers, drmoss, etc which do not represent a heavy capacitive load. an external resistor divider may be used to set the voltage to mid-rail while in the high impedance state. the pwmen outputs have an open-drain pull-up to intv cc and require an appropriate external pull-down resistor. this pin is intended to drive the enable pins of the mos - fet drivers that do not have three-state compatible pwm inputs. pwmen is low only when pwm is high impedance , and high at any other pwm state. power mosfet and schottky diode (optional) selection at least two external power mosfet s need to be selected : one n-channel mosfet for the top (main) switch and one or more n - channel mosfet (s) for the bottom (synchro - nous) switch. the number, type and on-resistance of all mo sfet s selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the mosfet will be used . a much smaller and much lower input capacitance mosfet should be used for the top mosfet in applications that have an output a pplica t ions i n f or m a t ion voltage that is less than one-third of the input voltage. in applications where v in >> v out , the top mosfets on- resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300khz. mosfet manufacturers have designed special purpose devices that provide reasonably low on-resistance with significantly reduced input capacitance for the main switch application in switching regulators. the peak-to-peak mosfet gate drive levels are set by the internal regulator voltage , v intvcc , requiring the use of logic-level threshold mosfets in most applications . pay close attention to the bv dss specification for the mosfets as well; many of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on-resistance, r ds(on) , input capacitance, input voltage and maximum output current. mosfet input capacitance is a combination of several components but can be taken from the typical gate charge cur ve included on most data sheets ( figure 8). the curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. figure 8. gate charge characteristic + ? v ds v in 3774 f08 v gs miller effect q in a b c miller = (q b ? q a )/v ds v gs v + ? the initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. the flat portion of the curve is the result of the miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load . the upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance . the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat ) is specified for a given v ds drain voltage, but can be adjusted for different v ds voltages by lt c3774 3774fb for more information www.linear.com/ltc3774
22 a pplica t ions i n f or m a t ion multiplying the ratio of the application v ds to the curve specified v ds values. a way to estimate the c miller term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated v ds voltage specified . c miller is the most important se - lection criteria for determining the transition loss term in the top mosfet but is not directly specified on mosfet data sheets . c rss and c os are specified sometimes but definitions of these parameters are not included. when the controller is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out v in synchronous switch duty cycle = v in C v out v in ? ? ? ? ? ? the power dissipation for the main and synchronous mosfets at maximum output current are given by: p main = v out v in i max ( ) 2 1 + ( ) r ds(on) + v in ( ) 2 i max 2 ? ? ? ? ? ? r dr ( ) c miller ( ) ? 1 v intvcc C v th(min) + 1 v th(min) ? ? ? ? ? ? ? ? ? f p sync = v in C v out v in i max ( ) 2 1 + ( ) r ds(on) where is the temperature dependency of r ds(on) , r dr is the effective top driver resistance (approximately 2 at v gs = v miller ), v in is the drain potential and the change in drain potential in the particular application . v th(min) is the data sheet specified typical gate threshold voltage specified in the power mosfet data sheet at the specified drain current. c miller is the calculated capacitance using the gate charge curve from the mosfet data sheet and the technique described above. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which peak at the highest input voltage. for v in < 20v, the high current efficiency generally improves with larger mosfets, while for v in > 20v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve , but = 0.005/c can be used as an approximation for low voltage mosfets. an optional schottky diode across the synchronous mosfet conducts during the dead time between the con - duction of the two large power mosfets . thi s pre vents the body diode of the bottom mosfet from turning on, storing charge during the dead time and requiring a reverse-recovery period which could cost as much as several percent in effi - ciency. a 2a to 8a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition loss due to their larger junction capacitance. mosfet driver selection gate driver ics, drmoss and power blocks with an interface compatible with the ltc3774' s three-state pwm outputs or the ltc3774' s pwm/ pwmen outputs can be used. always enable the power stage first , before the ltc3774 is enabled. c in and c out selection in continuous mode , the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in C v out ( ) ? ? ? ? 1/2 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. lt c3774 3774fb for more information www.linear.com/ltc3774
23 this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3774, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. ceramic capacitors are becoming very popular for small designs but several cautions should be observed . x7r , x5r and y5v are examples of a few of the ceramic materials used as the dielectric layer, and these different dielectrics have very different effect on the capacitance value due to the voltage and temperature conditions applied. physically, if the capacitance value changes due to applied voltage change, there is a concomitant piezo effect which results in radiating sound! a load that draws varying current at an audible rate may cause an attendant varying input volt - age on a ceramic capacitor, resulting in an audible signal . a secondary issue relates to the energy flowing back into a ceramic capacitor whose capacitance value is being reduced by the increasing charge. the voltage can increase a t a considerably higher rate than the constant current being supplied because the capacitance value is decreasing as the voltage is increasing! nevertheless, ceramic capacitors, when properly selected and used, can provide the lowest overall loss due to their extremely low esr. a small (0.1f to 1f) bypass capacitor, c in , between the chip v in pin and ground, placed close to the ltc3774, is also suggested. a 2.2 to 10 resistor placed between c in and v in pin provides further isolation. the selection of c out is driven by the required effective series resistance (esr). typically once the esr require - ment is satisfied the capacitance is adequate for filtering. the steady-state output ripple ( ?v out ) is determined by: ? v out ? i ripple esr + 1 8fc out ? ? ? ? ? ? where f = operating frequency, c out = output capacitance and ?i ripple = ripple current in the inductor. the output ripple is highest at maximum input voltage since ?i ripple increases with input voltage. the output ripple will be less than 50mv at maximum v in with ?i ripple = 0 .4i out(max) assuming: c out required esr < n ? r sense and c out > 1 8f ( ) r sense ( ) the emergence of very low esr capacitors in small , surface mount packages makes very small physical implementa - tions possible. the ability to externally compensate the switching regulator loop using the ith pin allows a much wider selection of output capacitor types . the impedance characteristic of each capacitor type is significantly differ - ent than an ideal capacitor and therefore requires accurate modeling or bench evaluation during design . manufacturers such as nichicon, nippon chemi-con and sanyo should be considered for high performance through-hole capacitors . the os-con semiconductor dielectric capacitors available from sanyo and the panasonic sp surface mount types have a good (esr)(size) product. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple( p-p) require- ment. ceramic capacitors from avx, taiyo yuden, murata and tdk offer high capacitance value and very low esr , especially applicable for low output voltage applications. in surface mount applications , multiple capacitors may have to be paralleled to meet the esr or rms current handling requirements of the application . aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations . new special polymer surface mount capacitors offer very low esr also but have much lower capacitive density per unit volume. in the case of tantalum , it is critical that the capacitors are surge tested for use in switching power supplies. several excellent choices are the avx tps , avx tpsv, the kemet t510 series of surface mount tantalums or the panasonic sp series of surface mount special polymer capacitors available in case heights ranging from 2mm to 4mm. other capacitor types include sanyo poscap, sanyo os-con, nichicon pl series and sprague 595d series. consult the manufacturers for other specific recommendations. a pplica t ions i n f or m a t ion lt c3774 3774fb for more information www.linear.com/ltc3774
24 a pplica t ions i n f or m a t ion differential amplifier the ltc3774 has true remote voltage sense capability . the sense connections should be returned from the load , back to the differential amplifier s inputs through a common, tightly coupled pair of pc traces. the differential amplifier rejects common mode signals capacitively or inductively radiated into the feedback pc traces as well as ground loop disturbances . the ltc3774 diffamp has high input impedance on v osns + pin. the output of the diffamp con - nects to the inverting input of the error amplifier internally. setting output v oltage the ltc3774 output voltage is set by an external feed - back resistive divider carefully placed across the output, as shown in figure 2. the regulated output voltage is determined by: v out = 0.6v ? 1 + r d1 r d2 ? ? ? ? ? ? to improve the frequency response , a feedforward ca - pacitor, c f1 , may be used. great care should be taken to route the v osns + line away from noise sources , such as the inductor or the sw line. to minimize the effect of the voltage drop caused by high current flowing through board conductance; connect v osns C and v osns + sense lines close to the ground and the load output respectively. external soft-start and tracking the ltc3774 has the ability to either soft-start by itself or track the output of another channel or external supply. when the controller is configured to soft-start by itself , a capacitor may be connected to its tk / ss pin or the internal soft-start may be used. the controller is in the shutdown state if its run pin voltage is below 1.22v and its tk/ss pin is actively pulled to ground in this shutdown state. if the run pin voltage is above 1.22v, the controller powers up. a soft-start current of 1.25a then starts to charge the tk/ ss soft-start capacitor. note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the tk/ss pin. the soft-start or tracking range is defined to be the voltage range from 0v to 0.6v on the tk/ss pin. the total soft-start time can be calculated as: t softstart = 0.6 ? c ss 1.25a regardless of the mode selected by the mode/pllin pin, the controller always starts in discontinuous mode up to tk/ss = 0.5v. between tk /ss = 0.5v and 0.565v, it will operate in for ced continuous mode and revert to the selected mode once tk /ss > 0.565v. the output ripple is minimized during the 65mv forced continuous mode window, ensuring a clean pgood signal. when the chan - nel is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the tk / ss pin. therefore, the volt - age ramp rate on this pin is determined by the ramp rate of the other supply s voltage. it is only possible to track another supply that is slower than the internal soft-start ramp. note that the small soft-start capacitor charging current is always flowing , producing a small offset error. to minimize this error , select the tracking resistive divider value to be small enough to make this error negligible . in order to track down another channel or supply after the soft-start phase expires, the ltc3774 is forced into continuous mode of operation as soon as v osns + is below the power good lower threshold regardless of the setting on the mode/pllin pin. however, the ltc3774 should always be set in forced continuous mode tracking down when there is no load. after tk/ss drops below 0.1v, the controller operates in discontinuous mode. the ltc3774 allows the user to program how its output ramps up and down by means of the tk/ss pin. through these pins, the output can be set up to either coincidentally or ratiometrically track another supplys output, as shown in figure 9. in the following discussions, v out2 refers to the ltc3774 s channel 2 as a slave and v out1 refers to channel 1 as a master. to implement the coincident track - ing in figure 9a, connect an additional resistive divider to v out1 and connect its mid-point to the tk/ss pin of the lt c3774 3774fb for more information www.linear.com/ltc3774
25 figure 9. two different modes of output voltage tracking figure 10. setup and coincident and ratiometric tracking time (9a) coincident tracking v out1 v out2 output voltage v out1 v out2 time 3774 f09 (9b) ratiometric tracking output voltage r3 r1 r4 r2 r3 v out2 r4 (10a) coincident tracking setup to v osns1 + pin to tk/ss2 pin to v osns2 + pin v out1 r1 r2 r3 v out2 r4 3774 f10 (10b) ratiometric tracking setup to v osns1 + pin to tk/ss2 pin to v osns2 + pin v out1 a pplica t ions i n f or m a t ion slave controller. the ratio of this divider should be the same as that of the slave controller s feedback divider shown in figure 10a. in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking in figure 9b, the ratio of the v out2 divider should be exactly the same as the master controllers feedback divider shown in figure 10b . by selecting different resis - tors, the ltc3774 can achieve different modes of tracking including the two in figure 9. so which mode should be programmed ? while either mode in figure 9 satisfies most practical applications, some trade-offs exist. the ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. under ratiometric tracking, when the master controllers output experiences dynamic excursion (under load transient, for example), the slave controller output will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric. lt c3774 3774fb for more information www.linear.com/ltc3774
26 a pplica t ions i n f or m a t ion intv cc (ldo) the ltc3774 features a true pmos ldo that supplies power to intv cc from the v in supply. intv cc powers the ltc3774 s internal circuitry . the ldo regulates the voltage at the intv cc pin to 5.5v when v in is greater than 6v. the ldo can supply a peak current of 20ma and must be bypassed to ground with a minimum of 4.7f ceramic capacitor or low esr electrolytic capacitor . no matter what type of bulk capacitor is used, an additional 0.1f ceramic capacitor placed directly adjacent to the intv cc and gnd pins is highly recommended. for applications where the main input power is 5v, tie the v in and intv cc pins together and tie the combined pins to the 5v input with a 1 or 2.2 resistor as shown in figure 11 to minimize the voltage drop caused by the gate charge current. this will override the intv cc linear regulator and will prevent intv cc from dropping too low due to the dropout voltage. on-time t on( min) of the ltc3774 (90ns with power stage), the input voltage and inductor value: ? i l(sc) = t on(min) ? v in l the resulting short-circuit current is: i sc = 1/ 3v sense(max) r sense ? 1 2 ? i l(sc) ? ? ? ? ? ? after a short, or while starting, make sure that the load current takes the folded-back current limit into account. phase-locked loop and frequency synchronization the ltc3774 has a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (vco) and a phase detector. this allows the turn-on of the top mosfet to be locked to the rising edge of an external clock signal applied to the mode/pllin pin. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators . this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen - tary current sources that charge or discharge the internal filter network . there is a precision 20a current flowing out of the freq pin. this allows the user to use a single resistor to gnd to set the switching frequency when no external clock is applied to the mode/pllin pin. the internal switch between the freq pin and the integrated pll filter network is on, allowing the filter network to be pre-charged at the same voltage as of the freq pin . the relationship between the voltage on the freq pin and operating frequency is shown in figure 12 and specified in the electrical characteristics table. if an external clock is detected on the mode/pllin pin, the internal switch mentioned above turns off and isolates the influence of the freq pin . note that the ltc3774 can only be synchronized to an external clock whose frequency is within range of the ltc3774 s internal vco . a simplified block diagram is shown in figure 13. figure 11. setup for a 5v input r vin 1 c in 3774 f11 5v c intvcc 4.7f + intv cc ltc3774 v in fault conditions: current limit and current foldback the ltc3774 includes current foldback to help limit load current when the output is shorted to ground. if the output falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one-third of the maximum value. foldback current limiting is not disabled during soft-start or tracking up. under short-circuit condi - tions with very low duty cycles , the lt c3774 will begin cycle skipping in order to limit the short-circuit current . in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short circuit ripple current is determined by the minimum lt c3774 3774fb for more information www.linear.com/ltc3774
27 figure 12. relationship between oscillator frequency and voltage at the freq pin figure 13. phase-locked loop block diagram v freq (v) 0.4 frequency (khz) 900 1100 1300 1.0 1.4 3774 f12 700 500 0.6 0.8 1.2 1.6 1.8 300 100 digital phase/ frequency detector vco 2.4v 5.5v 20a r set 3774 f13 freq sync external oscillator mode/pllin a pplica t ions i n f or m a t ion if the external clock frequency is greater than the inter - nal oscillators frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the filter network . when the external clock frequency is less than f osc , current is sunk continuously, pulling down the filter network. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the filter network is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the filter capacitor c lp holds the voltage. typically , the external clock ( on the mode/ pllin pin) input high threshold is 1.6v, while the input low threshold is 1v. using the clkout and phsmd pins in multiphase applications the ltc3774 features clkout and phsmd pins that allow multiple ltc3774 ics to be daisy chained together in multiphase applications. the clock output signal on the clkout pin can be used to synchronize additional ics in a 3-, 4-, 6-, 8- or 12-phase power supply solution feeding a single high current output, or even several outputs from the same input supply. the phsmd pin is used to adjust the phase relationship between channel 1 and channel 2, as well as the phase relationship between channel 1 and clkout. the phases are calculated relative to zero degrees, defined as the rising edge of pw m1. refer to the applications information section for more details on how to create multiphase applications. minimum on-time considerations minimum on-time , t on(min) , is the smallest time duration that the ltc3774 is capable of turning on the top mosfet. it is determined by internal timing delays, power stage timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v out v in f ( ) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the voltage ripple and current ripple will increase. lt c3774 3774fb for more information www.linear.com/ltc3774
28 the minimum on-time for the ltc3774 is approximately 90ns, with good pcb layout, minimum 30% inductor current ripple and at least 2mv ripple on the current sense signal. the minimum on-time can be affected by pcb switching noise in the voltage and current loop. as the peak sense voltage decreases the minimum on- time gradually increases this is of particular concern in for ced continuous applications with low ripple current at light loads . if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3774 circuits: 1) ic v in current, 2) mosfet driver current, 3) i 2 r losses, 4) topside mosfet transi - tion losses. 1 . the v in current is the dc supply current given in the electrical characteristics table. v in current typically results in a small (<0.1%) loss. 2. the mosfet driver current results from switching the gate capacitance of the power mosfets . each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from the driver supply to ground. the resulting dq/dt is a current out of the driver supply that is typically much larger than the control circuit current . in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. a pplica t ions i n f or m a t ion 3. i 2 r losses are predicted from the dc resistances of the fuse ( if used), mosfet, inductor and current sense re - sistor. in continuous mode, the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to obtain i 2 r losses. for example, if each r ds(on) = 10m , r l = 10m, r sense = 5m, then the total resistance is 25m. this results in losses ranging from 2% to 8% as the output current increases from 3a to 15a for a 5v output, or a 3% to 12% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet (s), and become significant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: t ransition loss = (1.7) v in 2 ? i o(max) ? c rss ? f other hidden losses such as copper trace and internal batter y resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m to 50m of esr. other losses including schottky conduction losses during dead time and inductor core losses generally account for less than 2% total additional loss. lt c3774 3774fb for more information www.linear.com/ltc3774
29 a pplica t ions i n f or m a t ion checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load ? esr, where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc-coupled and ac-filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response . assuming a predominantly second order system , phase margin and/ or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the typical application circuit will provide an adequate starting point for most applications. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined . the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop . placing a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop , so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance . a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. pc board layout checklist when laying out the printed circuit board , the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 14. check the following in the pc layout: 1. the intv cc decoupling capacitor should be placed immediately adjacent to the ic between the intv cc pin and gnd plane. a 1f ceramic capacitor of the x7r or x5r type is small enough to fit very close to the ic . an additional 4.7f to 10f of ceramic, tantalum or other very low esr capacitance is recommended in order to keep the internal ic supply quiet. lt c3774 3774fb for more information www.linear.com/ltc3774
30 2. place the feedback divider between the + and C terminals of cout. route v osns + and v osns C with minimum pc trace spacing from the ic to the feedback divider. 3. are the snsa + , snsd + and sns C printed circuit traces routed together with minimum pc trace spacing? the filter capacitors between snsa + , snsd + and sns C should be as close as possible to the pins of the ic. 4. do the (+) plates of c in connect to the drain of the topside mosfet as closely as possible ? this capacitor provides the pulsed current to the mosfet. 5. keep the switching nodes away from sensitive small- signal nodes (snsd + , snsa + , sns C , v osns + , v osns C ). ideally the pwm and switch nodes printed circuit traces should be routed away and separated from the ic and especially the quiet side of the ic. separate the high dv/ dt traces from sensitive small-signal nodes with ground traces or ground planes. 6. use a low impedance source such as a logic gate to drive the mode /pllin pin and keep the lead as short as possible. 7. the 47pf to 330pf ceramic capacitor between the i th pin and signal ground should be placed as close as possible to the ic. figure 14 illustrates all branch cur - rents in a switching regulator. it becomes very clear after studying the current waveforms why it is critical to keep the high switching current paths to a small physical size. high electric and magnetic fields will radiate from these loops just as radio stations transmit signals. the output capacitor ground should return to the negative terminal of the input capacitor and not share a com - mon ground path with any switched current paths. the left half of the cir cuit gives rise to the noise generated by a switching regulator. the ground terminations of the synchronous mosfet and schottky diode should return to the bottom plate(s) of the input capacitor(s) with a short isolated pc trace since very high switched currents are present. external opti-loop ? compensa- tion allows overcompensation for pc layouts which are not optimized but this is not the recommended design procedure . a pplica t ions i n f or m a t ion figure 14. branch current waveforms + r in v in v out c in + c out d1 sw2 sw1 l1 r sense r l 3774 f14 bold lines indicate high, switching currents. keep lines to a minimum length lt c3774 3774fb for more information www.linear.com/ltc3774
31 8. are the signal and power grounds kept separate ? the ic ground pin and the ground return of c intvcc must return to the combined c out (C) terminals. the v osns + and i th traces should be as short as possible. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 9. use a modified star ground technique: a low imped - ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the int v cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the gnd pin of the ic. design example as a design example of the front page circuit for a two- channel high current regulator, assume v in = 12v( nominal), v in = 20v(maximum), v out = 1.5v, i max = 60a, and f = 400khz (see front page schematic). the regulated output voltage is determined by : v out = 0.6v ? 1 + r b r a ? ? ? ? ? ? using a 10k 1% resistor from the v fb node to ground, the top feedback resistor is 15k. the frequency is set by biasing the freq pin to 0.75v (see figure 12). the inductance value is based on a 35% maximum ripple current assumption (10.5a per phase). the highest value of ripple current occurs at the maximum input voltage: l = v out f ? ? i l(max) 1 ? v out v in(max) ? ? ? ? ? ? ? ? this design will require 0.33h. the wrth 744301033, 0.32h inductor is chosen. at the nominal input voltage (12v), the ripple current will be: ? i l(nom) = v out f ? l 1 ? v out v in(nom) ? ? ? ? ? ? ? ? it will have 10a (33%) ripple. the peak inductor current will be the maximum dc value plus one-half the ripple current, or 35a per phase. the minimum on-time occurs at the maximum v in , and should not be less than 100ns (includes margin): t on(min) = v out v in(max) f = 1.5v 20v(400khz) = 187ns dcr sensing is used in this circuit . if c1 and c2 are chosen to be 220nf, based on the chosen 0.33h inductor with 0.32m dcr, r1 and r2 can be calculated as: r1 = l dcr ? c1 = 4.69k r2 = l dcr ? c2 ? 5 = 937 ? choose r1 = 4.64k and r2 = 931. a pplica t ions i n f or m a t ion lt c3774 3774fb for more information www.linear.com/ltc3774
32 the maximum dcr of the inductor is 0.34m. the v sense(max) is calculated as: v sense(max) = i peak ? dcr max = 12mv the current limit is chosen to be 15mv. if temperature variation is considered, please refer to inductor dcr sensing temperature compensation with ntc thermistor . the power dissipation on the topside mosfet can be easily estimated. choosing an infineon bsc050ne2ls mosfet results in : r ds(on) = 7 .1m? (max), v miller = 2.8v, c miller ? 108pf. at maximum input voltage with t j (estimated) = 75c: p main = 1.5v 20v 30a ( ) 2 1 + (0.005)(75 c C 25 c) [ ] ? 0.0071 ? ( ) + 20v ( ) 2 30a 2 ? ? ? ? ? ? 2 ? ( ) 108pf ( ) ? 1 5.5v C 2.8v + 1 2.8v ? ? ? ? ? ? 400khz ( ) = 599mw + 377mw = 976mw / phase for a 0.32m dcr, a short-circuit to ground will result in a folded back current of: i sc = 1/ 3 ( ) 15mv 0.00032 ? C 1 2 90ns(20v) 0.33h ? ? ? ? ? ? = 12.9a / phase an infineon bsc010ne2ls, r ds(on) = 1.1m?, is chosen for the bottom fet. the resulting power loss is: p sync = 20v C 1.5v 20v 30a ( ) 2 ? 1 + 0.005 ( ) ? 75 c C 25 c ( ) ? ? ? ? ? 0.0011 ? p sync = 1.14w/phase c in is chosen for an equivalent rms current rating of at least 13.7a. c out is chosen with an equivalent esr of 4.5m? for low output ripple. the output ripple in continu - ous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately : v oripple = r esr (?i l ) = 0.0045? ? 10a = 45mv p-p further reductions in output voltage ripple can be made by placing a 100f ceramic capacitor across c out . a pplica t ions i n f or m a t ion lt c3774 3774fb for more information www.linear.com/ltc3774
33 typical a pplica t ions 3774 ta02 ilim1 phsmd freq mode/pllin clkout intv cc v in ilim2 itemp2 ith2 v osns2 ? v osns2 + tk/ss2 hizb2 pwmen2 pwm2 run2 gnd itemp1 ith1 v osns1 ? v osns1 + tk/ss1 hizb1 pwmen1 pwm1 run1 gnd snsd1+ sns1? snsa1+ pgood1 pgood2 snsa2+ sns2? snsd2+ ltc3774 37.4k 10k r s1 20k r ntc1 100k r p1 43.2k r s2 20k r ntc2 100k r p2 43.2k 1f 2.2 30.1k 4.7f 10k v in run2 run1 intv cc 220pf 0.01f 22pf 15k 1.5nf 180f 10k 10k 100k 100k 10k 220pf 1.5nf v in v in 0.22f 0.22f 0.22f 0.22f v in phase v swh cgnd pgnd smod disb v cin v drv 22f 2.2f 1 2.2f 5v bias 22f 10k v in 7v to 14v intv cc intv cc 0.22f l1 0.33h 10k 10k 4.64k 931 c out1 100f 2 c out2 330f 3 1.5v/30a v out1 1.2v/30a v out2 v in phase v swh cgnd pgnd smod disb v cin v drv 22f 2.2f 1 2.2f 22f 0.22f l2 0.33h 10k 10k 4.64k 931 22pf 10k 10k c out3 100f 2 0.01f l1, l2: wrth 744301033 c out1,3 : murata grm31cr60j107me39l c out2,4 : sanyo 2r5tpe330m9 5v bias v in + fdmf6820a fdmf6820a pwm boot pwm boot + c out4 330f 3 + dual 1.5v/30a and 1.2v/30a ltc3774 converter with drmos and dcr temperature coefficient compensation lt c3774 3774fb for more information www.linear.com/ltc3774
34 typical a pplica t ions 3774 ta03 ilim1 phsmd freq mode/pllin clkout intv cc v in ilim2 itemp2 ith2 v osns2 ? v osns2 + tk/ss2 hizb2 pwmen2 pwm2 run2 gnd itemp1 ith1 v osns1 ? v osns1 + tk/ss1 hizb1 pwmen1 pwm1 run1 gnd snsd1+ sns1? snsa1+ pgood1 pgood2 snsa2+ sns2? snsd2+ ltc3774 37.4k 3.01k 1f 2.2 4.7f v in run1 intv cc 330pf 0.01f 22pf 10k 3.3nf 180f 10k 10k 10k 10k v in v in 0.22f 0.22f 0.22f 0.22f v in phase v swh cgnd pgnd smod disb v cin v drv 22f 2.2f 1 2.2f 5v bias 22f 10k v in 7v to 14v intv cc intv cc 0.22f l1 0.33h 10k 10k 4.64k 931 c out1 100f 4 1.2v/60a v out v in phase v swh cgnd pgnd smod disb v cin v drv 22f 2.2f 1 2.2f 22f 0.22f l2 0.33h 10k 10k 4.64k 931 c out2 330f 6 5v bias v in pwm boot fdmf6820a fdmf6820a pwm boot + l1, l2: wrth 744301033 c out1 : murata grm31cr60j107me39l c out2 : sanyo 2r5tpe330m9 2-phase 1.2v/60a ltc3774 converter with drmos lt c3774 3774fb for more information www.linear.com/ltc3774
35 typical a pplica t ions 2-phase 1.2v/60a ltc3774 converter with discrete drivers with mosfets 3774 ta04 ilim1 phsmd freq mode/pllin clkout intv cc v in ilim2 itemp2 ith2 v osns2 ? v osns2 + tk/ss2 hizb2 pwmen2 pwm2 run2 gnd itemp1 ith1 v osns1 ? v osns1 + tk/ss1 hizb1 pwmen1 pwm1 run1 gnd snsd1+ sns1? snsa1+ pgood1 pgood2 snsa2+ sns2? snsd2+ ltc3774 37.4k 3.01k 1f 2.2 4.7f v in run intv cc 330pf 0.01f 22pf 10k 3.3nf 180f 10k 10k 100k 100k v in v in 0.22f 4.7nf 1f 0.22f 0.22f 0.22nf 0.22f in v logic v cc boost gnd bg ts tg 10k intv cc v cc v in 7v to 14v v in intv cc l1 0.33h ltc4449 4.64k 931 c out1 4 c out2 330f 6 1.2v/60a v out 4.64k 931 22nf 2 bsc050ne2ls bsc010ne2ls 4.7nf 1f 0.22nf in v logic v cc boost gnd bg ts tg v cc 22nf 2 bsc050ne2ls bsc010ne2ls l2 0.33h 2.2 2.2 ltc4449 l1, l2: wrth 744301033 c out1 : murata grm31cr60j107me39l c out2 : sanyo 2r5tpe330m9 + + lt c3774 3774fb for more information www.linear.com/ltc3774
36 p ackage descrip t ion uhe package 36-lead plastic qfn (5mm 6mm) (reference ltc dwg # 05-08-1876 rev ?) please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 5.00 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 1 10 20 28 11 19 36 29 bottom view?exposed pad 4.50 ref 6.00 0.10 r = 0.125 typ 0.25 0.05 4.60 0.10 3.60 0.10 (uhe36) qfn 0410 rev ? 0.50 bsc 4.60 0.05 3.60 0.05 0.75 0.05 0.00 ? 0.05 0.200 ref recommended solder pad layout apply solder mask to areas that are not soldered 3.50 ref 0.40 0.10 0.70 0.05 0.50 bsc 4.50 ref 3.50 ref 4.10 0.05 5.50 0.05 5.10 0.05 6.50 0.05 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.10 typ lt c3774 3774fb for more information www.linear.com/ltc3774
37 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . r evision h is t ory rev date description page number a 01/14 replaced undervoltage lockout curve revised inductor dcr sensing temp comp and ntc compensated dcr sensing sections 6 17, 18 b 07/15 minor typographical changes changed intv cc pin description 3, 4, 6, 9 8 lt c3774 3774fb for more information www.linear.com/ltc3774
38 ? linear technology corporation 2013 lt 0715 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3774 typical a pplica t ion r ela t e d p ar t s dual phase 1.2v/30a ltc3774 converter with hot swap circuits on the input of each phase 3774 ta05 run1, 2 v in intv cc freq phsmd tk/ss1,2 i temp1,2 v osns1,2 + v osns1,2 ? i th1,2 i lim1,2 on1 cls gnd on2 ftmr1 fault1 fault2 ftmr2 snsd1 + sns1 ? snsa1 + pgood1 pgood2 snsa2 + sns2 ? snsd2 + clkout mode/pllin ltc3774 ltc4226 64.9k 10k 0.007 fdms86500dc d17 cmhz4690 0.007 fdms86500dc pwm2 hizb2 pwmen2 pwm1 hizb1 hizb1 hizb2 1f pwmen1 gnd 4.7f 10k 0.1f 37.4k 330pf l1, l2: wrth 744301033 coutcer1,2: murata grm31cr60j107me39l coutblk: sanyo 2r5tpe330m9 3.01k 2.2k 3.3nf 10k v cc2 sense2 gate2 out2 v cc1 sense1 gate1 out1 10k 10k 100pf 22f 25v v in 10v to 14v 150f 25v 2 5v bias v in1 v in2 + 30.1k 100pf 2.4m cmhz4690 1n4448hwt 1n4448hwt pwm v in boot phase v swh fdmf6820 drmos 5v bias 1 cgnd pgnd v cin v drv 0.22f l4 0.33h 2.2f 22f 25v 2 2.2f 0.22f 0.22f 0.22f 0.22f 931 4.64k 931 4.64k pwm v in boot phase v swh fdmf6820 drmos 5v bias 1 cgnd pgnd v cin v drv 0.22f 2.2f 22f 25v 2 2.2f c outcer1 100f 6.3v 2 c outcer1 330f 2.5v 6 v out 1.2v/30a l3 0.33h c outcer2 100f 6.3v 2 + 1n4448hwt 1n4448hwt 1f 10k v in1 v in2 37.4k part number description comments ltm4630 ltm4630-1a ltm4630-1b dual 18a or single 36a dc/dc module regulator 4.5v v in 15v, 0.6v v out 1.8v 1.5% max v out error over line,?load and temp C1a version: 0.8% max v out error over line, load and temp ltc3887 dual output multiphase step-down dc/dc controller with digital power system management and 0.5% accuracy 4.5v v in 24v, 0.5v v out 5.5v, analog control loop, 70ms start-up, i 2 c/pmbus interface with eeprom and 16-bit adc ltc3875 dual, multiphase synchronous controller with sub milliohm dcr sensing and temperature compensation 4.75v v in 38v, 0.6v v out 3.5v/5v excellent current share when paralleled lt c3861 dual, multiphase, synchronous step-down dc/dc controller with diff amp and t ri-state output drive operates with power blocks, drmos or external mosfet s 3v v in 24v ltc3855 dual output, 2-phase, synchronous step-down dc/dc controller with diff amp and dcr temperature compensation 4.5v v in 38v, 0.8v v out 12v pll fixed frequency 250khz to 770khz, lt c3856 single output 2-phase synchronous step-down dc/dc controller with diff amp and dcr t emperature compensation 4.5v v in 38v, 0.8v v out 5v pll fixed 250khz to 770khz frequency lt c3838 dual output, 2-phase, synchronous step-down dc/dc controller with diff amp and controlled on-t ime 4.5v v in 38v, 0.8v v out 5.5v pll, up to 2mhz switching frequency lt c3869/ ltc3869-2 dual output, 2-phase synchronous step-down dc/dc controller, with accurate current share 4v v in 38v, v out3 up to 12.5v pll fixed 250khz to 750khz frequency lt c4449 high speed synchronous n-channel mosfet driver v in up to 38v, 4v v cc 6.5v adaptive shoot-through protection, 2mm x 3mm dfn-8 lt c3774 3774fb for more information www.linear.com/ltc3774

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